1. Field of the Invention
The claimed invention relates to a semiconductor device and a method of fabricating the semiconductor device. More particularly, the claimed invention relates to a method of fabricating the semiconductor device wherein a hump on a subthreshold current slope is eliminated.
2. Discussion of the Related Art
A conventional n-channel metal oxide semiconductor field effect transistor (MOSFET) device is schematically illustrated in FIG. 1. A semiconductor substrate 10 is divided into an active region 11 and an isolation region 12. The substrate 10 is a p-type substrate doped with p-type impurities, such as Boron (B). The active region 11 forms a transistor, and the isolation region 12 electrically isolates the transistor from other transistors (not shown). It is known to form the isolation region 12 using a field oxide film which is formed by a local oxidation of silicon (LOCOS) method. It is also known to use a shallow trench isolation (STI) method to enhance the integrity of the semiconductor.
A gate electrode 13 is formed across a center of the active region 11. A source 14 and a drain 15 are formed in the active region 11. The source 14 and the drain 15 are separated by and are on opposing sides of the gate electrode 13. The source 14 and the drain 15 are doped with n-type impurities, such as phosphorus (P) or arsenic (As).
A disadvantage of using the trench isolation structure described above to fabricate n-channel transistors is that a hump occurs in a subthreshold current region. Electric fields concentrate along ends of a channel region (not shown), so that the threshold voltage is lower along the ends of the channel region than at a center portion (not shown) of the channel. The result is current leakage due to subthreshold current flows at the ends of the channel.
The areas where subthreshold current leakage occurs are indicated by A1 and A2 in FIG. 1. A first area Al is elliptically shaped with a first major axis parallel to a longitudinal axis of the substrate 10. A first minor axis of the first area Al lies on an axial axis of the substrate 10. A first region of the first area A1 spans the first major axis and encompasses a first portion of the gate electrode 13 and two equal portions of the isolation region 12, the two equal portions of the isolation region 12 being opposite the gate electrode 13. A second region of the first area A1 spans the first major axis and encompasses a second portion of the gate electrode 13, a first portion of the source 14 and a first portion of the drain 15, the first source portion being equal in surface area to the first drain portion.
A second area A2 is elliptically shaped with a second major axis parallel to the longitudinal axis of the substrate 10. A second minor axis of the second area A2 lies on the axial axis of the substrate 10. A first region of the second area A2 spans the second major axis and encompasses a third portion of the gate electrode 13, a second portion of the source 14 and a second portion of the drain 15, the second source portion being equal in surface area to the second drain portion. A second region of the second area A2 spans the second major axis and encompasses a fourth portion of the gate electrode 13 and two equal portions of the isolation region 12 being opposite the gate electrode 13.
Subthreshold current leakage occurs in the first area A1 and the second area A2. To solve this problem, it is known to increase the concentration of impurities, such as B at the ends of the channel region (not shown). In other words, a conventional solution to the hump occurrence is to increase the threshold voltage at the ends of the channel by implanting B ions into the sidewalls of the channel. However, this conventional solution results in decreased performance of the semiconductor device.